The present invention relates to a semiconductor memory technique and more specifically to a technique that may be effectively adapted to a system utilizing a non-volatile memory for electrically erasing and programming information and additionally to a technique that may be effectively adapted to a system using, for example, a flash memory.
The flash memory uses, as a memory cell, a non-volatile memory element consisting of a MOSFET of a double-layer gate structure including a control gate and a floating gate and is capable of changing a threshold voltage of the MOSFET to store information by changing a fixed amount of charges of the floating gate.
In this flash memory, change of threshold voltage due to the write and erase operation to the memory cell of course fluctuates among memory cells and also fluctuates for each operation even in the same memory cell and therefore the threshold voltage of the memory cell is distributed within a certain range after the write and erase operation. Moreover, in some memory cells, the threshold voltage of memory cell cannot be changed up to the desired level with a single cycle of the write and erase operations. Therefore, the flash memory often has a structure that a status register is generally provided therein and if write or erase operation is not successfully completed, such defective operation is stored as the write error or erase error.
In the side of CPU to give an instruction for write or erase operation to the flash memory, a sector including a memory cell which has generated an error is registered as a defective sector by referring to such status register and such sector is excluded thereafter from the effective memory area of data.
Although the threshold voltage cannot be changed up to the predetermined level in a certain memory cell which has generated an error even after the write and erase operations have been conducted many times, in many memory cells, the normal write operation can be realized by conducting the re-write operation after the erase operation is once conducted (hereinafter, such defective memory cell is called the accidentally defective memory cell). Particularly in a multi-level flash memory in which the data of 2-bits or more is stored in one memory cell, since the range of threshold voltage corresponding to each stored information is narrower than that of the binary memory cell, such accidental fault may be easily generated.
However, in the flash memory, the detail error condition of sectors including the bits having generated a write error has not been reflected on the status register. Therefore, the sectors having generated an error have all been registered as defective sectors and excluded from the effective memory area, and thereby the total memory capacity is reduced. Moreover, when a write error is generated, the alternative sector process to exchange such defective sector alternative sector is conducted. Therefore, a problem arises in which the time required for total write operation is extended.
It is an object of the present invention to provide a system utilizing an electrically erasable and programmable non-volatile semiconductor memory device, such as a flash memory, with a view toward preventing reduction of effective memory capacity due to an accidental write error and increasing the memory capacity for application as in the system.
It is another object of the present invention to provide a system utilizing an electrically erasable programmable non-volatile semiconductor memory device such as a flash memory, with a view toward reducing the number of times of the alternative sector process and reducing the time required for the total write operation.
The abovementioned and the other objects and novel features of the present invention will become apparent from description of this specification and the accompanying drawings.
Some principal aspects of the inventions disclosed in this specification can be summarized briefly as explained below.
In one aspect, there is provided, to a status register within a non-volatile semiconductor memory device chip, a bit indicating whether the normal write operation can be conducted by executing the write process again or not, and a controller for instructing the write process to such non-volatile semiconductor memory device issues an instruction to conduct again the write process to the same area depending on the bit condition of the status register.
In more detail, there is provided a memory system comprising a non-volatile semiconductor memory device, including a memory area including a plurality of non-volatile memory cells, a status register indicating the internal condition and an external terminal for outputting at least a part of the contents of the status register, and a controller for issuing an instruction to the non-volatile semiconductor memory device and conducting the process for the defective write process area. In this memory system, the status register is provided with a first bit to indicate whether the normal write process is possible or not by executing again the write process and the controller issues an instruction to conduct again the write process to the same area depending on the condition of the first bit.
According to the means explained above, a chance of normal write process increases, by reading the contents of the status register to conduct re-write process depending on the condition of bits, even in the memory cell which has once shown a fault and thereby reduction of effective memory capacity due to an accidental write error can be prevented.
The status register is preferably also provided with a second bit indicating whether the write process has been completed normally or not and the controller issues an instruction for re-write process depending on the condition of the first bit when the second bit indicates that the write process is not completed normally. Thereby, when the write process is completed normally, this write process can be completed immediately without checking the first bit which indicates possibility of normal write process by conducting again the write process.
The status register is preferably also provided with a third bit for indicating whether access from the external side of chip is possible or not and the controller issues an instruction, when the third bit indicates that access from external side is possible, to conduct again the write process depending on the condition of the first bit. Accordingly, whether the non-volatile semiconductor memory device is in the access-ready condition or not can be known accurately by reading the content of the status register.
Furthermore, the non-volatile semiconductor memory device is preferably provided with an external terminal for reflecting the condition of the third bit and the controller issues an instruction, when the signal at the external terminal indicates possibility of access from the external side, to conduct again the write process depending on the condition of the first bit. Accordingly, the controller can detect the end of write operation within the non-volatile semiconductor device without reading out the contents of the status register by monitoring the signal at the external terminal. Thereby, the total write operation period can be reduced by eliminating useless waiting time.
Moreover, the controller is also provided with a function to execute the process to replace the memory area in which the write process has not been completed normally with another memory area and therefore to execute, if the normal write process cannot be realized with the re-write process based on the condition of the first bit, the process to replace the memory area where the relevant normal write process has not been completed with the other memory area. Thereby, reduction of effective memory capacity due to an accidental write error can be reduced and the memory area where the normal write process cannot be realized even with the re-write process can be defined as a defective memory area and can be replaced with the other normal memory area.
In addition, the memory area where the normal write process is impossible may be replaced with another memory area in the case that the normal write process impossible even after the re-write process conducted on the basis of the first condition of the first bit and in the case that the second bit does not indicate the normal end of write process and the first bit is in the second condition. Thereby, an accidental write error and a non-accidental write error can be discriminated, the defective memory area can be replaced with the other normal memory area when a non-accidental write error is generated and the total write process period can be reduced.
When the memory area where the write process cannot be completed normally is replaced with the other normal memory area, the controller writes information indicating the defective memory area into a part of the memory area where the write process cannot be completed normally. Accordingly, read of erroneous information can be avoided and such information can be used for analysis of a fault.
In addition, at the time of replacing the memory area where the write process cannot be completed normally with the other memory area, the controller reads the information stored in the other memory area and then determines whether the relevant area is the defective memory area or not for the purpose of replacement of memory areas. Thereby, a useless write process can be eliminated, total write time can be shortened and useless power consumption can also be reduced.
Further, the controller executes the process to replace the relevant memory area with the other memory area if the write process cannot be completed normally even after the predetermined number of times of re-write process instructed depending on the condition of the first bit. Thereby, an endless loop in which the re-write operation is repeated upon erroneous determination of an accidental write error and abnormal extension of the time required for the write operation can be avoided.
Moreover, contents of the status register are read to the external terminal when a plurality of control signals supplied from the controller are combined as predetermined. Thereby, the controller can check the contents of the status register with a simplified process based on an output of the control signals.
A second principal aspect of the invention relates to a data processing system comprising a non-volatile semiconductor memory device including a memory area having a plurality of non-volatile memory cells, a status register indicating the internal condition and an external terminal for outputting at least a part of contents of the status register, and a controller for making access to such non-volatile semiconductor memory device, wherein the status register is provided with a first bit indicating whether the write process can be completed normally by executing again the write process, and the controller issues an instruction to conduct the write process again to the same area depending on the condition of the first bit.
According to the means explained above, a chance of normal write process even in the memory area where a fault is once generated can be increased when the controller reads the contents of the status register to issue an instruction for re-write process depending on the condition of the bit. Thereby, a reduction of effective memory capacity of the system due to an accidental write error can be prevented.
A third principal aspect of the invention relates to a data processing system comprising a non-volatile semiconductor memory circuit including a memory area having a plurality of non-volatile memory cells, a status register indicating the internal conditions and a terminal for outputting at least a part of contents of the status register, a memory device including a control circuit for issuing an instruction of write process to the non-volatile semiconductor memory circuit and conducting the process to the defective write area and a data processing device for making access to the memory device, wherein the status register is provided with a first bit indicating whether the write process can be completed normally by executing again the write process, and the control circuit issues an instruction to conduct again the write process to the same area depending on the condition of the first bit.
According to this means, a chance of normal write process even in the memory area where a fault is once generated can be increased when the control circuit reads the contents of status register and executes again the write process depending on the condition of the bit. Thereby, reduction of effective memory capacity of the system due to an accidental write error can be prevented and the share of data processing device can also be reduced.